Recently, semiconductor devices are being manufactured such that metal lines are formed on every layer of a multi-layered structure. The distance between vertically adjacent metal lines on an upper layer and a lower layer of the multi-layered structure is getting smaller. Additionally, the gap between metal lines placed on the same layer has been narrowed. For example, the distance between horizontally adjacent metal lines located on the same layer is getting smaller. As a result of these changes, semiconductor devices have become even more highly integrated.
The small distances between vertically or horizontally adjacent metal lines considerably affects the parasitic resistance and the parasitic capacitance between the metal lines in the multi-layered structure. The parasitic resistance and the parasitic capacitance are highly likely to deteriorate electrical characteristics of the associated device, especially, a VLSI (Very Large Scaled Integration) semiconductor device. Furthermore, the level of power consumption and the amount of signal leakage of the device may be increased due to an (RC) delay introduced by the parasitic resistance and capacitance.
Therefore, it is very important to develop a wiring technique for constructing a highly efficient multi-layered metal lines structure exhibiting a low RC value in a VLSI semiconductor device. In order to construct the highly efficient multi-layered metal lines structure, it is required to form a wiring layer by employing a metal having a low resistivity or to use an insulating film exhibiting a low permittivity.
Thus, research has been reported for reducing the capacitance of materials exhibiting low permittivities, (for example, SiO series in oxide of existing TEOS series). However, it is difficult to employ such materials in actual processing because the materials exhibiting low permittivities are not identified yet.
Alternatively, an air gap technique which serves to exhibit low permittivity in spite of applying a conventionally used material has been widely studied. Specifically, when employing air exhibiting a very low permittivity of 1, the parasitic capacitance seen at the multi-layered metal lines structure can be reduced in a VLSI semiconductor device and a low permittivity can be obtained by forming an air gap while using the existing TEOS (Tetra Ethyl Ortho Silicate) series.
However, the conventional air gap forming method has a problem in that an irregular air gap may be formed.
Referring to FIG. 1, a conventional air gap forming process in a semiconductor metal line manufacturing method is represented. A via plug 108 is formed between a lower metal line 102 and a top metal line 116. If the via plug 108 is misaligned with the lower metal line 102, a metal stringer A may remain around an air gap 114, thereby shorting the bottom and the top metal lines 102 and 116. In other words, a bad air gap may be formed because the via process is carried out after forming the air gap 114.